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The
Art of Computing Series – Development of PCI Express Technology
PCI
Express is the successor to PCI and AGP. Unlike PCI and AGP, which
are 32 and 64 bit parallel buses, PCI Express uses high-speed serial
link technology. PCI Express reflects an industry trend to replace
legacy, shared parallel buses with high-speed point-to-point serial
buses. The new bus technology will allow PCI Express transmission
rates to keep pace with processor and I/O advances.
PCI Express has the following advantages over PCI and AGP: PCI
Express is a serial technology providing scalable performance,
higher bandwidth (5-80 Gbps as compared to 1-2 Gbps) and
point-to-point linking dedicated to each device instead of the PCI
shared bus. In addition, PCI Express supports advanced power
management and native hot plug/hot swap support.
Since its inception in 1992, the PCI bus has become the I/O backbone
of nearly every computing platform in use. The original 33-MHz,
32-bit implementation delivers a peak theoretical bandwidth of 133
megabytes per second (MB/sec) or 1 Gbps.
An examination of PCI signaling technology reveals a multi-drop,
parallel bus that is reaching its performance limits. On a
multi-drop bus, all devices attached to it are connected to the same
set of wires. When a device is using the PCI bus, no other device
can communicate over the bus. All connected devices must share the
bus and wait their turn before sending or receiving data.
The multi-drop, shared PCI bus is hard-pressed to keep up with
today's devices. This situation worsens with upcoming peripheral
devices that have even higher data rates. For example, Gigabit
Ethernet requires a bandwidth of 125 MB/sec, which effectively
saturates the 133 MB/sec PCI bus. The IEEE 1394b bus has a maximum
bandwidth of 100 MB/sec, which can also saturate a standard PCI bus.
In addition, the PCI bus cannot be easily scaled up in frequency or
down in voltage, and the PCI bus does not support features such as
advanced power management or native hot plugging/hot swapping of
peripherals. As well, all of the available bandwidth of the PCI bus
is limited to one direction (send or receive) at a time.
The original PCI bus was designed to support 2D graphics,
high-performance disk drives, and local area networking. Not long
after PCI was introduced, the increasing bandwidth requirements of
3D graphics subsystems outstripped the 32-bit, 33-MHz PCI bus
bandwidth. As a result, Intel and several graphics suppliers created
the AGP specification which defined a dedicated, high-speed PCI bus
for graphics operations. The AGP bus offloaded graphics traffic from
the PCI system bus and freed up bandwidth for other communications
and I/O operations. In addition, Intel added dedicated USB 2.0 and
Serial ATA links to the Southbridge in its chip sets, further
reducing the I/O demands on the PCI bus.
PCI
Bus Block Diagram
Over the past decade, video performance requirements have
approximately doubled every two years. During this time, the
graphics bus has transitioned from PCI to AGP and from AGP to AGP2X,
AGP4X, and finally AGP8X. AGP8X operates at 2.134 gigabytes per
second (GB/sec). Despite this bandwidth, the progressive performance
demands on the AGP bus are putting considerable pressure on board
design and interconnection costs. As with the PCI bus, extending the
AGP bus becomes more difficult and expensive as frequencies
increase. Due to all of the bandwidth challenges, systems required a
replacement bus for the parallel PCI bus and AGP buses. Enter PCI
Express.
PCI Express Bus Block Diagram
The PCI Express architecture defines a high-performance,
point-to-point, scalable, serial bus. A PCI Express link consists of
dual simplex channels, each implemented as a transmit pair and a
receive pair for simultaneous transmission in each direction. Each
pair consists of two low-voltages, differentially driven pairs of
signals. A data clock is embedded in each pair, using an 8b/10b
clock-encoding scheme to achieve very high data rates.
The bandwidth of a PCI Express link can be scaled by adding signal
pairs to form multiple lanes between the two devices. The
specification supports x1, x4, x8, and x16 lane widths and stripes
the byte data across the links accordingly. Once the two agents at
each end of the PCI Express link negotiate lane widths and frequency
of operation, the striped data bytes are transmitted with 8b/10b
encoding.
The basic "x1" link has a peak raw bandwidth of 2.5 Gbps. Because
the bus is bi-directional (that is, data can be transferred in both
directions simultaneously), the effective raw data transfer rate is
5 Gbps. Note that PCI Express bandwidth is commonly expressed as
"encoded" bandwidth. PCI Express uses 8b/10b encoding, which encodes
8-bit data bytes into 10-bit transmission characters. This approach
improves the physical signal so that bit synchronization is easier,
design of receivers and transmitters is simplified, error detection
is improved, and control characters can be distinguished from data
characters. The "encoded" bandwidth of a basic x1 PCI Express lane
is 5 Gbps. However, a more accurate bandwidth figure is the "unencoded"
bandwidth, which is 80 percent of 5 Gbps, or 4 Gbps.
Because it is a point-to-point architecture, the entire bandwidth of
each PCI Express bus is dedicated to the device at the end of the
link. Multiple PCI Express devices can be active without interfering
with each other.
PCI Express has had the following impact on computer system
architectures: an x16 PCI Express link is replacing the AGP bus
between the graphics subsystem and the Northbridge. A PCI Express
variant link is replacing the link between the Northbridge and
Southbridge, relieving the bottleneck between peripheral I/O devices
and the Northbridge. There are multiple PCI Express links off the
Southbridge for the network interface controller (NIC), 1394
devices, and other peripherals.
The Southbridge will continue to support legacy PCI slots. Desktop
systems will have both PCI and PCI Express buses for a long time. To
minimize confusion during the transition, PCI cards cannot be
inadvertently inserted into PCI Express slots, nor can PCI Express
cards be inserted into legacy PCI slots. In addition, PCI Express
enables widespread adoption of Gigabit Ethernet, 10-Gigabit
Ethernet, 1394b, or other high speed devices in client systems. It
also supports increasing bandwidth requirements of graphics
subsystems.
By
TNS Research & Development Team
R&D Team Biography
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